//------------------------------------------------------------
//  Filename: aux_wraper.sv
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2019-05-11 12:54
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module AUX_WRAPER ( 
    input  wire        clk_100mhz,
    input  wire        reset_n,  

    input  wire [15:0] key_in,
    output wire [15:0] key_out,
    output wire        key_intr,

    input  wire [31:0] adc_ctrl,
    output wire [15:0] adc_data_read,
    output wire        adc_trans_over,

    output wire        adc_scl,
    inout  wire        adc_sda,

    input  wire [31:0] rtc_ctrl,
    output wire [15:0] rtc_data_read,
    output wire        rtc_trans_over,

    output wire        rtc_scl,
    inout  wire        rtc_sda,

    input  wire [31:0] eeprom_ctrl,
    output wire [15:0] eeprom_data_read,
    output wire        eeprom_trans_over,

    output wire        eeprom_scl,
    inout  wire        eeprom_sda,

    input  wire        load_time,  
    output wire [31:0] pcf8563_date,
    output wire [31:0] pcf8563_time,

    output wire [31:0] local_date,
    output wire [31:0] local_time,

    input  wire [31:0] gaoya_time, 
    input  wire [7:0]  gaoya_force,  
    input  wire [31:0] gaoya_ctrl_time,  
    input  wire [7:0 ] gaoya_ctrl_force,  

    output wire        motor_clk   ,

    output wire        dac_sclk    ,
    output wire        dac_sdata   ,
    output wire        dac_load    ,
    output wire        gaoya    
);
 
wire periphere_rstn;  
wire periphere_clk10k;  
wire periphere_clk1k ;  


PERIPH_CRG PERIPH_CRG_inst0( 
    .clk              ( clk_100mhz) ,
    .sys_rstn         ( reset_n   ) ,

    .periphere_rstn   ( periphere_rstn   ) ,  
    .periphere_clk300k( motor_clk        ) ,  
    .periphere_clk10k ( periphere_clk10k ) ,  
    .periphere_clk1k  ( periphere_clk1k  ) 
);      

key_proc key_proc_inst0(
    .clk            ( clk_100mhz        ) ,
    .rstn           ( reset_n           ) ,

    .clk_10k        ( periphere_clk10k  ) ,
    .key_in         ( key_in            ) ,
    .key_out        ( key_out           ) ,
    .key_intr       ( key_intr          )   
);

TOUCH_IIC touch_inst0( 
    .clk            ( clk_100mhz        ) ,
    .rst            ( ~reset_n          ) ,
    .clk_cp         ( clk_cp            ) ,

    .tp_ctrl        ( tp_ctrl           ) ,
    .tp_data_read   ( tp_data_read      ) ,
    .tp_trans_over  ( tp_trans_over     ) ,
 
    .tp_scl         ( tp_scl            ) ,
    .tp_sda         ( tp_sda            ) 
);
 
PCF8563_IIC rtc_inst0( 
    .clk            ( clk_100mhz        ) ,
    .rst            ( ~reset_n          ) ,

    .rtc_ctrl       ( rtc_ctrl          ) ,
    .rtc_data_read  ( rtc_data_read     ) ,
    .rtc_trans_over ( rtc_trans_over    ) ,

    .rtc_scl        ( rtc_scl           ) ,
    .rtc_sda        ( rtc_sda           ) ,

    .load_time      ( load_time         ) ,
    .pcf8563_date   ( pcf8563_date      ) ,
    .pcf8563_time   ( pcf8563_time      ) ,

    .local_date     ( local_date        ) ,
    .local_time     ( local_time        ) 
);  

MAX11645_IIC adc_inst0( 
    .clk            ( clk_100mhz        ) ,
    .rst            ( ~reset_n          ) ,

    .adc_ctrl       ( adc_ctrl          ) ,
    .adc_data_read  ( adc_data_read     ) ,
    .adc_trans_over ( adc_trans_over    ) ,

    .adc_scl        ( adc_scl           ) ,
    .adc_sda        ( adc_sda           ) 
);

GAOYA_PROC hv_inst0( 
    .clk              ( clk_100mhz      ) ,
    .rst              ( ~reset_n        ) ,

    .gaoya_time       ( gaoya_time      ) ,
    .gaoya_force      ( gaoya_force     ) ,
    .gaoya_ctrl_time  ( gaoya_ctrl_time ) ,
    .gaoya_ctrl_force ( gaoya_ctrl_force) ,
    
    .dac_sclk         ( dac_sclk        ) ,
    .dac_sdata        ( dac_sdata       ) ,
    .dac_load         ( dac_load        ) ,
    .gaoya            ( gaoya           ) 
);     

EEPROM_IIC  EEPROM_IIC_inst0( 
    .clk              ( clk_100mhz        ) ,
    .rst              ( ~reset_n          ) ,

    .eeprom_addr_size ( 1'b1              ) , 
    .eeprom_devid     ( 8'ha0             ) ,
    .eeprom_ctrl      ( eeprom_ctrl       ) ,
    .eeprom_data_read ( eeprom_data_read  ) ,
    .eeprom_trans_over( eeprom_trans_over ) ,

    .eeprom_sclk      ( eeprom_scl        ) ,
    .eeprom_sda       ( eeprom_sda        ) 
);      

endmodule
